AI/ML Verification of Microelectronic Integrity for High-Assurance Systems

During pre-release, until the topic opens on Dec 2, 2026, you may contact the topic author directly with technical questions. After that, questions go through the Topic Q&A on DSIP.

Develop an innovative, Artificial Intelligence / Machine Learning (AI/ML) driven methodology and prototype architecture capable of non-destructively verifying the physical and logical integrity of Integrated Circuits (ICs). The solution must reliably detect sub-nanometer, adversarial Hardware Trojans that evade conventional functional testing. This ensures absolute trust in microelectronics utilized in high-assurance communications, critical infrastructure, and secure data collection systems, explicitly including protections against data-layer subversion and unauthorized RF activation. [1] This effort bridges a critical gap between commercial supply chain illumination and physics-based national security hardware assurance. While current commercial offerings focus on firmware vulnerabilities and counterfeiting, they are blind to perfectly manufactured, sub-nanometer malicious logic such as Hardware Trojans. Furthermore, unlike existing programs such as DARPA AISS which operate in the pre-silicon design phase, this effort operates in the post-silicon verification phase assuming a "Zero Trust" posture.

The full objective, description, Phase I, II and III requirements and evaluation criteria are in the official topic on DSIP.