Defect Metrology and Charge Trapping Dynamics in Transfer-Doped Diamond Transistors
Projected CMMC Level Requirement
Technology Areas
Modernization Priorities
Keywords
Objective Summary
Develop an innovative, non-destructive diamond semiconductor defect metrology technique and laboratory-scale apparatus to identify, quantify, determine location in the device, and energetically characterize charge traps that cause current collapse in surface-channel diamond transistors.
The full objective, description, Phase I, II and III requirements and evaluation criteria are in the official topic on DSIP.
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Book Free 30-Min ConsultationTopic details summarized from the official DoW SBIR/STTR solicitation. The full solicitation text, phase descriptions, evaluation criteria and submission requirements are published by the Department of War at dodsbirsttr.mil. Defense Grant Writers does not host or reproduce solicitation content.