DOD · OSD Open STTR · Phase I
OSW26TZ06-NV005

Development of Ultrafast Nonvolatile Memory Based on Sliding Ferroelectricity in Moiré Polar Homostructures

Parent BAA: DoW STTR 2026 BAA · Release 6
Opens
Sep 23, 2026
Closes
Oct 21, 2026
Deadline
—
Component
OSD

Projected CMMC Level Requirement

Level 1

Technology Areas

  • None

Modernization Priorities

  • Advanced Materials
  • Microelectronics
  • Quantum Science

Keywords

  • Sliding ferroelectricity
  • moiré superlattice
  • van der Waals materials
  • nonvolatile memory
  • twistronics
  • two-dimensional materials
  • ferroelectric domains
  • graphene field-effect transistor
  • transition metal dichalcogenides
  • low-power memory
  • high-endurance memory
  • polar homostructures.

Objective Summary

Develop ultrafast, high-endurance, nonvolatile memory technology based on sliding ferroelectricity in polar moiré van der Waals homostructures.

The full objective, description, Phase I, II and III requirements and evaluation criteria are in the official topic on DSIP.

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Topic details summarized from the official DoW SBIR/STTR solicitation. The full solicitation text, phase descriptions, evaluation criteria and submission requirements are published by the Department of War at dodsbirsttr.mil. Defense Grant Writers does not host or reproduce solicitation content.